This invention relates to arbiters and selectors, and networks of the same.
In general, an arbiter is a logic circuit having two input ports and one output port; and in operation, messages are passed from either input port to the output port. One prior art arbiter is described, for example, in the U.S. Pat. No. 4,251,879 issued Feb. 17, 1981 to Becky J. Clark, who is also the inventor in the present application.
Also in general, a selector is a logic circuit having one input port and two output ports, and in operation, messages are passed from the one input port to a selectable one of the two output ports. One prior art selector is described, for example, in U.S. Pat. No. 4,237,447 issued Dec. 2, 1980 to the same Becky J. Clark.
Now a limitation which the above-cited arbiters and selectors have is that they only operate on bit serial messages. That is, the messages which pass from their input port to their output ports do so only one bit at a time. Thus, the maximum baud rate at which those arbiters and selectors operate is relatively low.
To increase that baud rate, one might try arranging a number of the above-cited arbiters and selectors in parallel. But a problem with such a parallel arrangement is that multiple bits would not pass through the parallel paths in synchronization with each other. This is because the arbiters choose one of their input paths or the other in a random fashion when requests arrive on both input ports simultaneously. Thus, multiple bits sent from one source through a parallel arrangement of the above-cited arbiters and selectors would reach their destination in an unpredictable and highly scrambled fashion.
Accordingly, a primary object of the present invention is to provide an improved selector.
Another object of the invention is to provide a selector which passes multiple bits in parallel from its input port to its output ports.